The present invention relates to a bus bridge and to a method for interfacing an out-of-order bus with multiple ordered buses.
A bus bridge is used to interface different types of buses such as ordered buses and out-of-order buses. In Out-of-order buses a single transaction (read or write) is split into an address phase and a data phase. The address and data phases are spaced in time and the order in which the data phases are issued may differ from the order in which the address phases were issued. Both of the address and data phases include one or more clock cycles.
A many-to-one bus bridge may interface a single out-of-order bus and multiple ordered buses. Each ordered bus interface has a buffer and control logic for compensating for timing differences between the different buses and for facilitating protocol conversions.
The duplication of buffers and control logic for each ordered bus interface is not efficient. Thus, there is a growing need to provide an efficient bus bridge and a method for interfacing an out-of-order bus and multiple ordered buses.